PPU

The description is divided into 2 parts (according to the modules), so as not to torment the browser with large pictures.

• PPU1
• PPU2

PPU SoC boundary (external signals)

Interface between the whole PPU (PPU1 + PPU2, treated as one block) and the rest of the die. A net is external when at least one non-PPU block touches it: ClkGen, SM83Core/Arbiter, MMIO, the OAM RAM macro, pads or a global rail. Nets that run exclusively between PPU1 and PPU2 are excluded from these tables (per-part port tables: PPU1 signals, PPU2 signals).

Directions are from the PPU side. Net names are the dmgcpu.v pin names. The wiring was cross-checked against HDL/soc/dmgcpu.v (all instances); the table rows are grouped by the SoC block on the other end.

Clocks and reset — from ClkGen

Clock topology: ClkGen → PPU2 (cclk, clk6, n_reset2). PPU2 then synthesizes the clocks the other side uses: ppu_clk (= cclk) and ppu_rd/ppu_wr (re-driven soc_rd/soc_wr) are sent to PPU1 and MMIO; n_ppu_clk, h_restart, vclk2… stay PPU1↔PPU2 internal. PPU1 has no direct ClkGen contact — every clock/PPU strobe reaches it from PPU2 (ppu_clk, n_ppu_clk, ppu_rd, ppu_wr, n_ppu_hard_reset).

PPU-generated clocks, strobes, resets and interrupts — to MMIO / Arbiter

CPU bus and address decode — Core / Arbiter / MMIO

VRAM interface — Arbiter, MA/MD pads (external LH5164 SRAM)

The PPU-internal VRAM address bus nma[12:0] is PPU1↔PPU2 only (both halves drive it with inverting tristates) — the chip pins carry n_ma (PPU1 → MA pads), which is the inverse-hold version of the same address.

DMA and OAM-access control — MMIO / Arbiter

OAM RAM macro — PPU2 only (chip-internal RAM block, HDL/soc/oam.v)

PPU2 is the sole master of the OAM RAM: the nets below run exclusively between PPU2 and OAM (no CPU/MMIO direct access).

LCD driver — PPU1 to pads

Global rails

Excluded — PPU1 ↔ PPU2 internal nets (reference)

Nets that never leave the PPU pair (also listed in the per-part tables):

• PPU1 → PPU2: ff42, ff43 (SCY/SCX access), fexx, FF40_D1..D3 (LCDC bits), h[7:0], v[7:0], in_window, vbl, vclk2, n_ppu_reset, ppu1_ma0 (= PPU2 ma0), bp_sel, bp_cy, tm_cy, oam_addr_ck, oam_rd_ck, oam_xattr_latch_cck, obj_prio_ck, oam_mode3_nrd, oam_mode3_bl_pch, n_dma_phi2_latched, nma[12:0] (bidir). (ppu_mode3, sp_bp_cys also reach the Arbiter → boundary table above.)

• PPU2 → PPU1: n_ppu_clk, ppu_mode2, stop_oam_eval, h_restart, obj_color, obj_prio, sprite_x_flip, sprite_x_match, FF43_D0..D2 (SCX bits), nma[12:0] (bidir). (ppu_clk, ppu_rd/ppu_wr, n_ppu_hard_reset also reach MMIO/Arb → boundary table above.)

Clock cadence checks (testbench)

• The Icarus environment (HDL/soc/icarus/ppu/ppu_env.v) instantiates the real ClkGen netlist: osc_ena/clk_ena/osc_stable = 1, reset = the test reset, oscillator n_clk_in = ~ck1 (64 ns tick). PPU1/PPU2 are wired exactly as in dmgcpu.v for every boundary net listed above.

• ClkGen inputs cpu_wr, cpu_mreq, test_1 are tied to 0 in the testbench; in the netlist they feed only the sync / chip-select outputs (cpu_wr_sync, ext_cs_en) and not the clock outputs (cclk, clk6, n_reset2, clk1..9), so the clock cadence seen by PPU1/PPU2 is identical to the running SoC. MMIO/Arbiter are represented by the test's bus tasks (cpu_write/cpu_read drive a/d/ffxx/arb_fexx_ffxx/strobe timing; DMA inputs dma_run, vram_to_oam, oam_dma_wr… are held inactive or driven by the test).

• Resulting dot cadence verified by the regression suite: 456-tick line with mode 2 = 80 ticks and mode 3 = ~173 ticks (BG-only), 160 LD pixels per line, VBlank at LY≥144 and V wrap 153→0 (waves.md, tests 1–9).

Simulation

A regression testbench that runs the real PPU1/PPU2 netlists (with behavioral VRAM/OAM models) lives in HDL/soc/icarus/ppu — see its Readme and waves.md.