SHARP DMG CPU Cells Library

dmg_cells

dmglib

The cells shown are only part of the SHARP cell library (name?), other cell types will probably be found in other chips of this era.

Symmetry group

In general, the dihedral group 4 (D4) is used for cells
By agreement among all researchers ident position of the cell (e) - when the ground is on the left
As part of modules, cells are usually simply reflected relative to the vertical axis e <-> b (for ClkGen and Ser modules, cells are additionally rotated “sideways”)
As part of macro cells (memory), cells can be arranged arbitrarily, as is more convenient

Dih4_cycle_graph

Dual-rail CLK

Sequential elements (latch, dff) are presented in two variants: with single-rail CLK and with dual-rail CLK (CLK + complement CLK). Where dual-rail CLK is used, the suffix comp is used in the cell name.

Cells list

The following are all cell types, in alphabetical order. The names of cells by @msinger (http://iceboy.a-singer.de/doc/dmg_cells.html) are shown in parentheses (where the correspondence is not obvious) The topology is not complete (m1 is missing in some places), but it is sufficient to understand the cell architecture for reimplementation.

and

and3

and4

aon (AO1)

2 AND to 2 OR Non-Inverting.

aon

aon22 (AO2)

2+2 AND to 3 OR Non-Inverting.

aon22

aon222 (AO3)

2+2+2 AND to 4 OR Non-Inverting.

aon222

aon2222 (AO4)

2+2+2+2 AND to 5 OR Non-Inverting.

aon2222

aon222222 (AO6)

2+2+2+2+2+2 AND to 7 OR Non-Inverting.

aon222222

bufif0 (TRI_BUF_IF0)

bufif0

cnt (TFFD)

cnt

cnt_tran

dmg_cnt

const

dffr - Posedge DFF With Single-rail CLK Synchronous Dual-rail Inverse Polarity Reset Q/NQ Output (DFFR_B2)

The #res input is fed separately to the Master and Slave MUX so that synchronous reset can be done. But usually #res1 and #res2 are connected externally, so the DFF becomes with asynchronous reset. The dual-rail ck/cck signals are obtained locally by demultiplexing the CLK input signal.

dffr