Skip to content

DMG-CPU Research

SoC SM83 PCB Methods Tests GitHub ↗

Home/wiki/DMG CPU Core/Rails

Rails

Connections between the Decoders 1/2 and Decoder3

locator_rails1

rails1

Connections between top and bottom

locator_rails2

rails2

Cross1

locator_cross1

cross1

Cross2

locator_cross2

cross2

↑ DMG CPU Core Back to top ↑Source on GitHub ↗

DMG-CPU Research

Die-level reverse engineering of the Nintendo DMG-CPU SoC of the original Game Boy: from silicon photographs to a die-perfect Verilog netlist.

Unofficial research project, not affiliated with or endorsed by Nintendo. Terminology conventions are defined in the readme.

Wiki

SoC overview
SM83 core
Reference PCB
Research methods
Datasets

Verilog

Icarus suites
SM83 suite waves
PPU suite waves
APU suite waves
GTKWave skill

Links

GitHub repository ↗
Deroute utility ↗
dmg-schematics ↗
gb-research (Gekkio) ↗
issues ↗