ALU

The SM83 ALU is a regular 8-bit CLA adder.

See: https://www.youtube.com/watch?v=WItAXzrfPrE&list=PLBDB2c4Mp7hBLRcEpE19yyHB-zKzsyp_4&index=20

A note from the future: although in this section individual modules are referred to by a single name (e.g. Sums), most modules actually fulfill a hybrid role. For example, the module for obtaining G/P terms is also used for logical operations (as it comes naturally from the nature of G/P). The ALU is not yet fully understood, so some of the signals have "cryptologic" names.

ALU Inputs

Inputs from Decoder2/3

The control ALU inputs from decoders 2/3 are listed separately.

ALU Outputs

Internal Wires

NOR-8

8-NOR:

The result of the nor8 operation is the AllZeros signal. This is often required to calculate the Z flag.

Top Part

The paired construction that looks like a Christmas tree is actually two 4-bit Carry Lookahead Generators (module5).

In between is the small logic (8 AND gates implementing logical XOR operation out of G/P terms), and above the 8 "Sum" blocks (module6), which give the result of the ALU (Res).

module5 (4-bit CLA Generators, x2)

The gaps contain AND gates that implement a logical XOR operation based on the G/P Terms outputs (x/h).

module6 (Sums)

8 identical modules.

Middle Part (G/P Terms)

8 identical modules.

Bottom Part

Contains shifter, random logic and the flag register (F).

Shifter

Contains 8 dynamic comb logic modules (ANDs-to-NORs + CLK2), multiplexing DV operand(2) to outputs (ca[7:0], active low output):

Comb1 (bit 7)	Comb2 (bits 6-1)	Comb3 (bit 0)

The output from the dynamic combinatorial logic is stored on the DLatch (see G/P Terms module).

Random Logic

The lower part contains many dynamic NAND trees, the inputs for which come from all sides and also from module2 instancies.

Tree numbering is topological (how they are arranged on the chip). ALU trees 0,3-6,8,9 are responsible for preprocessing operand 1 for SET/RES opcodes (CB table) as well as DAA (decimal correction). Because of the topological numbering of the trees, they don't go in order, which is a bit ugly.

Random logic (14 NAND trees):

The result is an AND-to-NOR tree (using alu_0 as an example):

(the dynamic part is not shown in the picture)

ALU Operand1 Preprocessing (trees 0,3-6,8-10)

ALU trees 0,3-6,8-10 are responsible for preprocessing operand 1 for SET/RES opcodes (CB table) as well as DAA (decimal correction). Because of the topological numbering of the trees, they don't go in order, which is a bit ugly.

Cond Code Check (tree 11)

ALU tree 11 deals with code checking for conditional instructions (NZ/Z/NC/C)

Flags Logic (trees 1,2,7,12)

TBD.

Carry In (tree 13)

TBD.

Flags

bc

Regular memory cell (latch) with write enable (x28/x29). It also contains a Precharge FET for the dynamic logic which is above (input d). By the way the input d in the drawing is marked in inverse polarity, because the current hypothesis is that the signal bc is in direct polarity, and the operation which forms the signal d (AOI) gives the result in inverse polarity.

ALU_to_bot

A regular memory cell (latch), for storing the TempZ = zbus[7] value (msb). The signal CLK4 acts as WriteEnable.